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Inter-Integrated Circuit
SLTF
SLTF
or SHTF2
?
SLTF2
Clear
IICIF
Y
FACK?
N
Flow
Y
Master
Mode
N
Chart1
(See Note 2.)
?
TX
Tx/Rx
?
RX
Y
Arbitration
Lost
?
N
Last Byte
Transmitted
?
Y
Last Byte
to be Read
?
Y
Clear
ARBL
N
N
RXAK=0
?
Y
N
Y
Second-Last
Byte to be Read
?
N
N
IAAS=1
?
Y
Y
IAAS=1
?
N
Address Transfer
Y
End of
Addr Cycle
(Master Rx)
?
N
Read Data
from IICD
and Soft CRC
Y
(Read)
Read Data
from IICD
(See Note 1.)
SRW=1
?
N (Write)
RX
TX/RX
?
TX
Clear
IICIF
Set TXACK =1,
Set FACK = 0
Generate Stop
Signal (MST = 0)
and Soft CRC
Set TXAK to
ACK from
Receiver
?
Y
Proper Value ,
Clear IICIF
N
Clear IICIF
Write Next
Byte to IICD
Set TXAK to
Proper Value
Set TX Mode,
Write Data
Read Data from
IICD and Soft CRC
Y
Tx Next Byte
to IICD
Switch to
Rx Mode
Clear
IICIF
Set TXAK to
Proper Value ,
Clear IICIF
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
(MST = 0)
Read Data from
IICD and Store
Read Data
from IICD and
Store
Dummy Read
from IICD
RTI
NOTES:
1. If a general call or SIICAEN is enabled, a check must be done to determine whether the received address was a general-call address (0x00) or a SMbus-device,
default address. If the received address was one of them, it must be handled by user software.
2. Flow chart 1 means Figure 9-13 on page 178 . Typical I 2 C Interrupt Routine.
3. As receive side the second data reading should be done after ninth SCL cycle.
Figure 9-14. Typical I 2 C SMBus interrupt routine
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
179
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